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英文文献及翻译
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你可能喜欢求一篇关于数控机床主传动系统的英文文献，做毕业设计用，有关的就行。_百度作业帮
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求一篇关于数控机床主传动系统的英文文献，做毕业设计用，有关的就行。
求一篇关于数控机床主传动系统的英文文献，做毕业设计用，有关的就行。
Ordinary lathe main transmission system design specificationA: design, the design of a plain lathe main transmission system, complete transmission series for 8-12.Second, the design purpose:1: through the design practice, master machine main transmission system design method.2: cultivate comprehensive use of mechanical drawing, mechanical design, structure and process related knowledge of engineering design.3: training manual, atlas, relevant material and design standards.4: improving technology and prepare technical document.5: is the graduation design teaching implementation of technical preparation.Third, the design content and the basic requirements:Design content:(a) movement design(1) transmission scheme design (concentration), separate transmission(2) rotational speed range(3) than: archduke ratio, and mixing ratio and dukedoms than male(4) to determine the structure and structured: (1) : former vice driving less dense than before and after after dredging, (2) solution: a speeding level increases, b: using variable transmission mechanism and branch(5) rendering speed diagram (1) : former slow velocity rush (2) after the former acc: after the rushSanjiaodai (6) : sure. The variable pinion gear group(7) draw transmission system(2) power design(1) the transmission shaft, and the calculation speed: each gear(2) trunnion shaft(3) gear module(4) : spindle, trunnion (before), after the diameter size in front, before a roughers.tousegravity-flotation (stretched quantity: 100-120), support form, reasonable span of supports L(3) structure design(4) check a gear (minimum), check spindle (ocsm), torque,Basic requirements:1: according to the requirement of design project, reasonable size, sports and determine relevant parameters.2: correct use structured, speed diagram design tools, serious scheme analysis.3: the correct use manual, standard, design patterns must conform to the state standards. Say to the book with engineering terms, the words written neatly, smooth succinct.4:1 - main transmission system to control electrical tools principle chart 1.Four, design parameters:The biggest diameter serial processing spindle speed series (r/min) drive motor power and synchronous speed1 ,355,250,180 400mm125,90 4.5 kw, 1500r/min,2 ,250,180 400mm125,90,45, 4kw 1500r/min,3 320mm 00,710,500,360250,180,125,90,63,42, 4kw 1500r/min,4 320mm 0,500,360,250180,125,90,63,45,22, 1500r/min 3kw,5 320mm 00,800,630,5004kw 1500r/min, 400,320,250,200,160,1006 320mm 0,630,500,400,320250,200,160,100,63, 1500r/min 3kw,The second group of parameter selection (as design data),Five, the motion parameters design(1) transmission scheme design (choice) transmission(2) rotational speed range(3) choose than mixing(4) to determine the structure and structured:(5) rendering speed: shown below(6) determine the pinion gear speed groupThe calculation of the first expand group pinion gearThe first group of expanding ratio, respectively:Therefore the minimum number of gear ratio for querying, take, and is,2 basically the group is respectively: ratio,Therefore the minimum number of gear ratio for querying, there is,3 the second expansion ratio of group,Therefore the gear combinations, at least in the table, and there,(7) transmission chart is as follows:Six, the dynamic parameter design(1) the calculation speed transmissionThe axis of rotation axis calculation, the calculation, for 125r/min speed.Each axis calculation speed is as follows:1 2 3 serial electric shaftComputing speed (r/min) 1440 125The minimum gear turns as follows: the computationAxis number and minimum gear combinations, 1 (22) 2 (22) 3 (20) (50),Computing speed (r/min)
125(2) the output power of the shafts(3) of the shaft torqueN.m (m)N.m (m)N.m (m)N.m (m)Seven, the design and selection of trunnion keysA: the shaft, and take into the formula:Have, however, roundChoose the spline:Axis, and take into two: formula:Have, however, roundChoose the spline:Axis, and take into three: formula:跨文化管理英文文献阅读报告_百度文库
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跨文化管理英文文献阅读报告
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你可能喜欢求一篇关于CPLD的英文文献翻译_百度作业帮
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求一篇关于CPLD的英文文献翻译
求一篇关于CPLD的英文文献翻译
Reliability Processing Of The Circuits In CPLD Design Abstract:This paper studies on the elimination of the competitive and narrow pulse interference and on the reliability of the reset circuit in CPLD design .Methods of additional trigger ,delay superposition ,and larger loop feedback are introduced .The corresponding examples are discussed detailedly .The reliability problems of the circuits in CPLD design are solved effectively .CPLD has been widely used in the design of electronic circuits and system because of its flexibility ,modifiability ,and short development cycle .There inevitably exist unreliable factors in CPLD design such as competitive interference ,narrow pulse interference ,and false tigger [1 .This paper studies the reliability problems by examples and introduces corresponding process methods .The results are satisfied.Ⅰ.Anti-interference Design of Complicated Circuits A complicated pulse signal generator can be implemented in block diagram as shown in fig..1.Where ,all blocks can be integrated in CPLD except the waveform data storage ,in which all turn time and corresponding state are stored.An EPROM can be used ,two bytes for each turn time and state .The active crystal oscillator is usually used for CPLD as the clock signal ,because its frequency is high,the divider is necessary to reduce the clock signal to an allowed frequency .Counter Ⅰis a timer unit in each period.Counter Ⅱ is a address pointer ,indicating the address to be accessed currently .The date latch records the turn of the output signal.The encoder produces the triggering signals of the data latch an the state latch.The periodic control signal is reset of the divider and two counters,and is clock of additive counter to control high address of the EPROM if the output signal is different between periodic.Counter Ⅰ counts from 0 to each periodic .When its counted value equals the data in the data latch ,the output of the comparer turns high level,and the output trigger is triggered,he output signal turns following the output of the state latch.At the same time,the NAND gate opens,the clock signal acts on the counter Ⅱand the encoder .At the rising edge,the counter Ⅱplus by Ⅰ,the data latch and state latch lock mew data,the next turn time and state from ERROM .The output of the comparer recovers low level.An output signal turn and data preset completed.Apparently ,as long as the time and the state for each turn is preset in the waveform data storage,the right signal output can be achieved.However,the above-mentioned signals are out of order because of the existence of the competitive interference ,as shown in figure 2.Where ,the data latch is B=005(binary system of12-bit)and the state latch is ST=0 when counter Ⅰoutputs C=002.It means that INST,the output signal ,is to turn to low level at the time when C=005 But the simulation shows that INST turns in advance ,i.e,the output signal is error .The reason is competitive interference ,which appears on CMP,the output of the comparer ,when counter Ⅰchanges from 003 to 004 .Meanwhile,because of the competitive interference ,the NAND gate opens in advance and A,value of Counter Ⅱ,plusses by 1 ,The time sequences of WR0 and WR1 ,outputs of the encoder ,are error ,In fig 2,CLKCLK2 is output of the divider and CK1 is the output of the NAND gate. 上传我的文档
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